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813001agi www.icst.com/products/hiperclocks.html rev. a september 2, 2005 1 integrated circuit systems, inc. ics813001i d ual vcxo w /3.3v, 2.5v lvpecl f emto c lock ? pll g eneral d escription the ics813001i is a dual vcxo + femtoclock? multiplier designed for use in discrete pll loops. two selectable external vcxo crystals allow the device to be used in multi-rate appli- cations, where a given line card can be switched, for example, between 1gb ethernet (125mhz system reference clock) and 1gb fibre channel (106.25mhz system reference clock) modes. of course, a multitude of other applications are also possible such as switching between 74.25mhz and 74.175824mhz for hdtv, switching between sonet, fec and non fec rates, etc. the ics813001i is a two stage device ? a vcxo followed by a femtoclock pll. the femtoclock pll can multiply the crystal frequency of the vcxo to provide an output frequency range of 40.83mhz to 640mhz, with a random rms phase jitter of less than 1ps (12khz ? 20mhz). this phase jitter performance meets the requirements of 1gb/ 10gb ethernet, 1gb, 2gb, 4gb and 10gb fibre channel, and sonet up to oc48. the femtoclock pll can also be bypassed if frequency multiplication is not required. for testing/debug purposes, de-assertion of the output enable pin will place both q and nq in a high impedance state. f eatures ? one 3.3v or 2.5v lvpecl output pair ? two selectable crystal oscillator interfaces for the vcxo, one differential clock or one lvcmos/lvttl clock inputs ? clk1/nclk1 supports the following input types: lvpecl, lvds, lvhstl, sstl, hcsl ? crystal operating frequency range: 14mhz - 24mhz ? vco range: 490mhz - 640mhz ? output frequency range: 40.83mhz - 640mhz ? vcxo pull range: 100ppm (typical) ? supports the following applications (among others): sonet, ethernet, fibre channel, hdtv, mpeg ? rms phase jitter @ 622.08mhz (12khz - 20mhz): 0.84 (typical) ? supply voltage modes: v cc /v cco 3.3v/3.3v 3.3v/2.5v 2.5v/2.5v ? -40c to 85c ambient operating temperature ? available in both, standard and rohs/lead-free compliant packages hiperclocks? ic s b lock d iagram vcxo 1 0 (default) 1 1 0 0 0 1 pd vco 490-640mhz 0 1 feedback divider m output divider n m2:m0 000 16 001 20 010 22 011 24 100 25 (default) 101 32 110 40 111 mr n2:n0 000 1 001 2 010 3 011 4 (default) 100 5 101 6 110 8 111 12 p in a ssignment ics813001i 24-lead tssop 4.40mm x 7.8mm x 0.92mm package body g package top view vco_sel n0 n1 n2 v cco q nq v ee v cca v cc xtal_out1 xtal_in1 1 2 3 4 5 6 7 8 9 10 11 12 clk_sel1 clk_sel0 oe m2 m1 m0 clk1 nclk1 clk0 vc xtal_in0 xtal_out0 24 23 22 21 20 19 18 17 16 15 14 13 vco_sel clk_sel0 clk_sel1 clk0 clk1 nclk1 vc m2 m1 m0 n2 n1 n0 oe pullup pullup pullup q nq xtal_in0 xtal_out0 xtal_in1 xtal_out1 pulldown pulldown pullup pullup pullup pullup pulldown pulldown pulldown pulldown
813001agi www.icst.com/products/hiperclocks.html rev. a september 2, 2005 2 integrated circuit systems, inc. ics813001i d ual vcxo w /3.3v, 2.5v lvpecl f emto c lock ? pll t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k ? ? ? 1l e s _ o c vt u p n ip u l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p t c e l e s o c v 3 , 21 n , 0 nt u p n ip u l l u p . 4 = e u l a v t l u a f e d . s n i p t c e l e s r e d i v i d t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l 42 nt u p n in w o d l l u p 5v o c c r e w o p. n i p y l p p u s t u p t u o 7 , 6q n , qt u p u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 8v e e r e w o p. n i p y l p p u s e v i t a g e n 9v a c c r e w o p. n i p y l p p u s g o l a n a 0 1v c c r e w o p. n i p y l p p u s e r o c 1 1 2 1 , 1 t u o _ l a t x 1 n i _ l a t x t u p n i , t u p t u o e h t s i 1 t u o _ l a t x . e c a f r e t n i l a t s y r c t n a n o s e r l e l l a r a p . t u p n i e h t s i 1 n i _ l a t x 3 1 4 1 , 0 t u o _ l a t x 0 n i _ l a t x t u p n i , t u p t u o e h t s i 0 t u o _ l a t x . e c a f r e t n i l a t s y r c t n a n o s e r l e l l a r a p . t u p n i e h t s i 0 n i _ l a t x 5 1c vt u p n i. t u p n i e g a t l o v l o r t n o c o x c v 6 10 k l ct u p n in w o d l l u p. t u p n i k c o l c l t t v l / s o m c v l 7 11 k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 8 11 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 0 2 , 9 11 m , 0 mt u p n in w o d l l u p . 5 2 = e u l a v t l u a f e d . s n i p t c e l e s r e d i v i d k c a b d e e f . s l e v e l e c a f r e t n i l t t v l / s o m c v l 1 22 mt u p n ip u l l u p 2 2e ot u p n ip u l l u p t u p t u o e h t , w o l n e h w . e v i t c a s i t u p t u o e h t , h g i h n e h w . e l b a n e t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e t a t s e c n a d e p m i h g i h a n i s i 3 20 l e s _ k l ct u p n in w o d l l u p . 3 e l b a t o t r e f e r . s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p t c e l e s k c o l c 4 21 l e s _ k l ct u p n ip u l l u p : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r t able 3. c ontrol i nput f unction t able s t u p n i 1 l e s _ k l c0 l e s _ k l ct u p n i d e t c e l e s 00 0 k l c 01 1 k l c n , 1 k l c 10 0 l a t x 11 1 l a t x
813001agi www.icst.com/products/hiperclocks.html rev. a september 2, 2005 3 integrated circuit systems, inc. ics813001i d ual vcxo w /3.3v, 2.5v lvpecl f emto c lock ? pll t able 4a. p ower s upply dc c haracteristics , v cc = v cca = v cco = 3.3v5%, ta = -40c to 85c a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o (lvpecl) continuous current 50ma surge current 100ma package thermal impedance, ja 70c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. t able 4c. p ower s upply dc c haracteristics , v cc = v cca = v cco = 2.5v5%, ta = -40c to 85c t able 4b. p ower s upply dc c haracteristics , v cc = v cca = 3.3v5%, v cco = 2.5v5%, ta = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v o c c e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 0 3 1a m i a c c t n e r r u c y l p p u s g o l a n a 0 1a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v o c c e g a t l o v y l p p u s t u p t u o 5 7 3 . 25 . 25 2 6 . 2v i e e t n e r r u c y l p p u s r e w o p 0 3 1a m i a c c t n e r r u c y l p p u s g o l a n a 0 1a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 7 3 . 25 . 25 2 6 . 2v v a c c e g a t l o v y l p p u s g o l a n a 5 7 3 . 25 . 25 2 6 . 2v v o c c e g a t l o v y l p p u s t u p t u o 5 7 3 . 25 . 25 2 6 . 2v i e e t n e r r u c y l p p u s r e w o p 5 2 1a m i a c c t n e r r u c y l p p u s g o l a n a 0 1a m
813001agi www.icst.com/products/hiperclocks.html rev. a september 2, 2005 4 integrated circuit systems, inc. ics813001i d ual vcxo w /3.3v, 2.5v lvpecl f emto c lock ? pll t able 4e. lvpecl dc c haracteristics , ta = -40c to 85c t able 4c. lvcmos / lvttl dc c haracteristics , ta = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c . v 2 - t able 4d. d ifferential dc c haracteristics , ta = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i 1 k l c v n i v = c c v 5 6 4 . 3 = v 5 2 6 . 2 r o 0 5 1a 1 k l c n v n i v = c c v 5 6 4 . 3 = v 5 2 6 . 2 r o 5a i l i t n e r r u c w o l t u p n i 1 k l c v n i v , v 0 = c c v 5 6 4 . 3 = v 5 2 6 . 2 r o 5 -a 1 k l c n v n i v , v 0 = c c v 5 6 4 . 3 = v 5 2 6 . 2 r o 0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o cv e e 5 . 0 +v c c 5 8 . 0 -v v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i . v s i 1 k l c n , 1 k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a i l p p a d e d n e e l g n i s r o f : 2 e t o n c c . v 3 . 0 + l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i v c c v 3 . 3 =0 . 2v c c 3 . 0 +v v c c v 5 . 2 =7 . 1v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i v c c v 3 . 3 =3 . 0 -8 . 0v v c c v 5 . 2 =3 . 0 -7 . 0v c ve g a t l o v l o r t n o c o x c v 0v c c v i h i t u p n i t n e r r u c h g i h , 1 m , 0 m , 2 n 0 l e s _ k l c , 0 k l c v c c v = n i v 5 6 4 . 3 = v 5 2 6 . 2 r o 0 5 1a , 2 m , 1 n , 0 n 1 l e s _ k l c , l e s _ o c v v c c v = n i v 5 6 4 . 3 = v 5 2 6 . 2 r o 5a i l i t u p n i t n e r r u c w o l , 1 m , 0 m , 2 n 0 l e s _ k l c , 0 k l c v c c , v 5 2 6 . 2 r o v 5 6 4 . 3 = v n i v 0 = 5 -a , 2 m , 1 n , 0 n 1 l e s _ k l c , l e s _ o c v v c c , v 5 2 6 . 2 r o v 5 6 4 . 3 = v n i v 0 = 0 5 1 -a i c v v ? c t n e r r u c t u p n i c n i pv c c v 5 2 6 . 2 r o v 5 6 4 . 3 =0 0 1 -0 0 1a
813001agi www.icst.com/products/hiperclocks.html rev. a september 2, 2005 5 integrated circuit systems, inc. ics813001i d ual vcxo w /3.3v, 2.5v lvpecl f emto c lock ? pll t able 5b. ac c haracteristics , v cc = v cca = 3.3v5%, v cco = 2.5v5%, ta = -40c to 85c t able 5a. ac c haracteristics , v cc = v cca = v cco = 3.3v5%, ta = -40c to 85c t able 5c. ac c haracteristics , v cc = v cca = v cco = 2.5v5%, ta = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o1 = l e s _ o c v3 8 . 0 40 4 6z h m t ) ? ( t i j ; ) m o d n a r ( , r e t t i j e s a h p s m r 1 e t o n ) z h m 0 2 - z h k 2 1 ( z h m 8 0 . 2 2 64 8 . 0s p f o c v e g n a r k c o l o c v l l p 0 9 40 4 6z h m t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 5 20 0 5s p c d oe l c y c y t u d t u p t u o 1 n3 47 5% n 1 8 42 5% . e c a f r e t n i l a t s y r c a g n i s u r e t t i j e s a h p : 1 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o1 = l e s _ o c v3 8 . 0 40 4 6z h m t ) ? ( t i j ; ) m o d n a r ( , r e t t i j e s a h p s m r 1 e t o n ) z h m 0 2 - z h k 2 1 ( z h m 8 0 . 2 2 67 8 . 0s p f o c v e g n a r k c o l o c v l l p 0 9 40 4 6z h m t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 5 20 0 5s p c d oe l c y c y t u d t u p t u o 1 n3 47 5% n 1 8 42 5% . e c a f r e t n i l a t s y r c a g n i s u r e t t i j e s a h p : 1 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o1 = l e s _ o c v3 8 . 0 40 4 6z h m t ) ? ( t i j ; ) m o d n a r ( , r e t t i j e s a h p s m r 1 e t o n ) z h m 0 2 - z h k 2 1 ( z h m 8 0 . 2 2 62 . 1s p f o c v e g n a r k c o l o c v l l p 0 9 40 4 6z h m t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 5 20 0 5s p c d oe l c y c y t u d t u p t u o 1 n3 47 5% n 1 8 42 5% . e c a f r e t n i l a t s y r c a g n i s u r e t t i j e s a h p : 1 e t o n
813001agi www.icst.com/products/hiperclocks.html rev. a september 2, 2005 6 integrated circuit systems, inc. ics813001i d ual vcxo w /3.3v, 2.5v lvpecl f emto c lock ? pll t ypical p hase n oise at 622.08mh z @ 3.3v 622.08mhz rms phase jitter (random) 12khz to 20mhz = 0.84ps (typical) o ffset f requency (h z ) dbc hz n oise p ower 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m phase noise result by adding sonet oc-12 filter to raw data raw phase noise data oc-12 filter ? ? ?
813001agi www.icst.com/products/hiperclocks.html rev. a september 2, 2005 7 integrated circuit systems, inc. ics813001i d ual vcxo w /3.3v, 2.5v lvpecl f emto c lock ? pll o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v sw i n g p arameter m easurement i nformation 3.3v c ore /3.3v lvpecl o utput l oad ac t est c ircuit scope qx nqx lvpecl 2v -1.3v0.165v o utput d uty c ycle /p ulse w idth /p eriod v ee 3.3v c ore /2.5v lvpecl o utput l oad ac t est c ircuit rms p hase j itter phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power d ifferential i nput l evels scope qx nqx lvpecl 2v -0.5v 0.125v v ee 2.5v c ore /2.5v lvpecl o utput l oad ac t est c ircuit v cc, v cca, v cco v cc, v cca, v cco t pw t period t pw t period odc = x 100% q nq scope qx nqx lvpecl 2.8v0.04v -0.5v 0.125v v ee v cc, v cca v cco v cmr cross points v pp v cc nclk1 clk1 v ee 2v
813001agi www.icst.com/products/hiperclocks.html rev. a september 2, 2005 8 integrated circuit systems, inc. ics813001i d ual vcxo w /3.3v, 2.5v lvpecl f emto c lock ? pll a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics813001i provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca , and v cco should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 resistor along with a 10f and a .01 f bypass capacitor should be connected to each v cca . p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v or 2.5v .01 f v cc figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 2. s ingle e nded s ignal d riving d ifferential i nput of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. w iring the d ifferential i nput to a ccept s ingle e nded l evels v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vcc
813001agi www.icst.com/products/hiperclocks.html rev. a september 2, 2005 9 integrated circuit systems, inc. ics813001i d ual vcxo w /3.3v, 2.5v lvpecl f emto c lock ? pll vcxo c rystal s election choosing a crystal with the correct characteristics is one of the most critical steps in using a voltage controlled crystal oscillator (vcxo). the crystal parameters affect the tuning f igure 3. vcxo o scillator c ircuit v c - control voltage used to tune frequency c v - varactor capacitance, varies due to the change in control voltage c l1, c l2 - load tuning capacitance used for fine tuning or centering nominal frequency c s1, c s2 - stray capacitance caused by pads, vias, and other board parasitics range and accuracy of a vcxo. below are the key variables and an example of using the crystal parameters to calculate the tuning range of the vcxo. oscillator v c c v c s1 c l1 c s2 c l2 c v xtal vcxo (internal) optional ? ? ? ? ? control voltage t able 6. e xample c rystal p arameters l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f n y c n e u q e r f l a n i m o n 4 14 2z h m f t e c n a r e l o t y c n e u q e r f 0 2 m p p f s y t i l i b a t s y c n e u q e r f 0 2 m p p e g n a r e r u t a r e p m e t g n i t a r e p o 00 7c c l e c n a t i c a p a c d a o l 2 1f p c o e c n a t i c a p a c t n u h s 4f p c , 1 c 2 o i t a r y t i l i b a l l u p 0 2 20 4 2 r s ee c n a t s i s e r s e i r e s t n e l a v i u q e 0 2 l e v e l e v i r d 1w m c 5 2 @ g n i g a r a e y r e p 3 m p p n o i t a r e p o f o e d o m l a t n e m a d n u f
813001agi www.icst.com/products/hiperclocks.html rev. a september 2, 2005 10 integrated circuit systems, inc. ics813001i d ual vcxo w /3.3v, 2.5v lvpecl f emto c lock ? pll l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c w o l _ v e c n a t i c a p a c r o t c a r a v w o lv c v 0 =5 1f p c h g i h _ v e c n a t i c a p a c r o t c a r a v h g i hv c v 3 . 3 =4 . 7 2f p t able 7. v aractor p arameters f ormulas ( ) ( ) ()( ) low v s l low v s l low v s l low v s l low c c c c c c c c c c c c c _ 2 2 _ 1 1 _ 2 2 _ 1 1 + + + + + + + ? + + = ( ) ( ) ()( ) high v s l high v s l high v s l high v s l high c c c c c c c c c c c c c _ 2 2 _ 1 1 _ 2 2 _ 1 1 + + + + + + + ? + + = 6 0 1 0 0 1 0 10 1 2 1 1 2 1 ) ( ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? + ? ? = c c c c c c c c tpr range pull t otal high low ?c low is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance. c low determines the high frequency component on the tpr. ?c high is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance. c high determines the low frequency component on the tpr. absolute pull range (apr) = total pull range ? (frequency tolerance + frequency stability + aging) e xample c alculations using the tables and figures above, we can now calculate the tpr and apr of the vcxo using the example crystal parameters. for the numerical example below there were some assumptions made. first, the stray capacitance (c s1 , c s2 ), which is all the excess capacitance due to board parasitic, is 4pf. second, the expected lifetime of the project is 5 years; hence the inaccuracy due to aging is 15ppm. third, though many boards will not require load tuning capacitors (c l1 , c l2 ), it is recommended for long-term consistent performance of the system that two tuning capacitor pads be placed into every design. typical values for the load tuning capacitors will range from 0 to 4pf. tpr = 106ppm apr = 106ppm ? (20ppm + 20ppm + 15ppm) = 51ppm the example above will ensure a total pull range of 106 ppm with an apr of 51ppm. many times, board designers may select their own crystal based on their application. if the application requires a tighter apr, a crystal with better pullability (c0/c1 ratio) can be used. also, with the equations above, one can vary the frequency tolerance, temperature stability, and aging or shunt capacitance to achieve the required pullability. c low = (0 + 4 p ? + 15 p ? ) (0 + 4 p ? + 15 p ? ) (0 + 4 p ? + 15 p ? ) (0 + 4 p ? + 15 p ? ) = 9.5p ? c high = (0 + 4 p ? + 27.4 p ? ) (0 + 4 p ? + 27.4 p ? ) (0 + 4 p ? + 27.4 p ? ) (0 + 4 p ? + 27.4 p ? ) = 15.7p ? 1 ? ? ? ? ? ? ? ? ? ? 1 2 220 ( 1 + 9.5 p ? 4 p ? ) 2 220 ( 1 + 15.7 p ? 4 p ? ) 1 ? tpr = = 10 6 = 212ppm
813001agi www.icst.com/products/hiperclocks.html rev. a september 2, 2005 11 integrated circuit systems, inc. ics813001i d ual vcxo w /3.3v, 2.5v lvpecl f emto c lock ? pll f igure 4c. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 4b. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 4d. h i p er c lock s clk/nclk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to4e show inter- face examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested f igure 4a. h i p er c lock s clk/nclk i nput d riven by ics h i p er c lock s lvhstl d river here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 4a, the input termination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 4e. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1 zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
813001agi www.icst.com/products/hiperclocks.html rev. a september 2, 2005 12 integrated circuit systems, inc. ics813001i d ual vcxo w /3.3v, 2.5v lvpecl f emto c lock ? pll t ermination for 3.3v lvpecl o utput v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical ter- mination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. there- fore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 transmission lines. f igure 5b. lvpecl o utput t ermination f igure 5a. lvpecl o utput t ermination matched impedance techniques should be used to maxi- mize operating frequency and minimize signal distor- tion. figures 5a and 5b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compat- ibility across all printed circuit and clock component pro- cess variations. i nputs : c rystal i nput : for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k resistor can be tied from xtal_in to ground. clk i nput : for applications not requiring the use of a clock input, it can be left floating. though not required, but for additional protection, a 1k resistor can be tied from the clk input to ground. clk/nclk i nput : for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k resistor can be tied from clk to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. vc input pin - do not float, must be biased. r ecommendations for u nused i nput and o utput p ins o utputs : lvpecl o utput all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
813001agi www.icst.com/products/hiperclocks.html rev. a september 2, 2005 13 integrated circuit systems, inc. ics813001i d ual vcxo w /3.3v, 2.5v lvpecl f emto c lock ? pll t ermination for 2.5v lvpecl o utput figure 6a and figure 6b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to ter- minating 50 to v cc - 2v. for v cco = 2.5v, the v cco - 2v is very close to ground level. the r3 in figure 6b can be eliminated and the termination is shown in figure 6c. f igure 6c. 2.5v lvpecl t ermination e xample r2 50 zo = 50 ohm vcco=2.5v r1 50 zo = 50 ohm + - 2.5v 2,5v lvpecl driv er f igure 6b. 2.5v lvpecl d river t ermination e xample vcco=2.5v r1 50 r2 50 zo = 50 ohm r3 18 2,5v lvpecl driv er zo = 50 ohm + - 2.5v f igure 6a. 2.5v lvpecl d river t ermination e xample r2 62.5 2.5v 2,5v lvpecl driv er r3 250 zo = 50 ohm zo = 50 ohm r4 62.5 2.5v + - r1 250 vcco=2.5v
813001agi www.icst.com/products/hiperclocks.html rev. a september 2, 2005 14 integrated circuit systems, inc. ics813001i d ual vcxo w /3.3v, 2.5v lvpecl f emto c lock ? pll p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics813001i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics813001i is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 130ma = 450.45mw ? power (outputs) max = 30mw/loaded output pair total power _max (3.465v, with output switching) = 450.45mw + 30mw = 480.5mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 70c/w per table 8 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.481w * 65c/w = 116.3c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 8. t hermal r esistance ja for 24- pin tssop, f orced c onvection ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 70c/w 65c/w 62c/w
813001agi www.icst.com/products/hiperclocks.html rev. a september 2, 2005 15 integrated circuit systems, inc. ics813001i d ual vcxo w /3.3v, 2.5v lvpecl f emto c lock ? pll 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 7. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco - 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco _max - v oh_max )) /r l ] * (v cco_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco _max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 7. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
813001agi www.icst.com/products/hiperclocks.html rev. a september 2, 2005 16 integrated circuit systems, inc. ics813001i d ual vcxo w /3.3v, 2.5v lvpecl f emto c lock ? pll r eliability i nformation t ransistor c ount the transistor count for ics813001i is: 3948 t able 9. ja vs . a ir f low t able for 24 l ead tssop ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 70c/w 65c/w 62c/w
813001agi www.icst.com/products/hiperclocks.html rev. a september 2, 2005 17 integrated circuit systems, inc. ics813001i d ual vcxo w /3.3v, 2.5v lvpecl f emto c lock ? pll p ackage o utline - g s uffix for 24 l ead tssop t able 10. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n4 2 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 7 . 70 9 . 7 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
813001agi www.icst.com/products/hiperclocks.html rev. a september 2, 2005 18 integrated circuit systems, inc. ics813001i d ual vcxo w /3.3v, 2.5v lvpecl f emto c lock ? pll t able 11. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. the aforementioned trademarks, hiperclocks and femtoclocks are trademarks of integrated circuit systems, inc. or its subsidiari es in the united states and/or other countries. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t i g a 1 0 0 3 1 8 s c ii g a 1 0 0 3 1 8 s c ip o s s t d a e l 4 2e b u tc 5 8 o t c 0 4 - t i g a 1 0 0 3 1 8 s c ii g a 1 0 0 3 1 8 s c ip o s s t d a e l 4 2l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l i g a 1 0 0 3 1 8 s c il i g a 1 0 0 3 1 8 s c ip o s s t " e e r f - d a e l " d a e l 4 2e b u tc 5 8 o t c 0 4 - t f l i g a 1 0 0 3 1 8 s c il i g a 1 0 0 3 1 8 s c ip o s s t " e e r f - d a e l " d a e l 4 2l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s f l n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n

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